"The problem is the opportunities sometimes are just not available to them. That's what we've got to address."
The tradeoff is complexity. The microcode must be carefully arranged so that the instructions in delay slots are either useful setup for both paths, or at least harmless if the redirect fires. Not every case is as clean as RETF. When a PLA redirect interrupts an LCALL, the return address is already pushed onto the microcode call stack (yes, the 386 has a microcode call stack) -- the redirected code must account for this stale entry. When multiple protection tests overlap, or when a redirect fires during a delay slot of another jump, the control flow becomes hard to reason about. During the FPGA core implementation, protection delay slot interactions were consistently the most difficult bugs to track down.
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The grid lines on the visualization represent a tree structure underneath. Every region is a node. When a node splits, it creates four children. The root node covers the entire space. Leaf nodes (nodes with no children) hold the actual points.